1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a stacked gate type flash semiconductor memory device, and a method for manufacturing the same.
2. Background of the Related Art
FIG. 1 is a diagram showing a cross-sectional view of a structure of a related art semiconductor memory device. FIGS. 2a through 2e are diagrams showing cross-sectional views illustrating a related art method for manufacturing the semiconductor memory device.
Referring to FIG. 1, the related art semiconductor memory device is a stacked gate type flash memory device. On a substrate 1, a tunnel oxide layer 2a and a floating gate 3a are formed to be stacked. On the entire surface of the floating gate 3a, an interpoly dielectric layer 4a and a control gate 5a are formed to be stacked. Insulating sidewalls 8 are formed on both sides of the control gate 5a and the floating gate 3a. While a lightly-doped source region 7 is formed at either of both sides of the floating gate 3a, heavily-doped source and drain regions 9 are formed in the substrate 1 at both the sides of the floating gate 3a. On the entire surface, there is formed an interlayer insulating layer 10 having contact holes. Each of the contact holes is formed on each of the heavily-doped source and drain regions 9. A wiring layer 11 is formed to contact with each of the heavily-doped source and drain regions 9 via the contact holes.
A related art method for manufacturing the semiconductor memory device of FIG. 1 will be explained with reference to the accompanying drawings. First, a first thin oxide layer 2 is formed on a substrate 1, as shown in FIG. 2a. Then, a first polysilicon layer 3 is formed on the first oxide layer 2. Next, the first oxide layer 2 and the first polysilicon layer 3 are patterned to form a thin tunnel oxide layer 2a and a floating gate 3a.
Subsequently, a second oxide layer 4 and a second polysilicon layer 5 are successively formed on the entire surface, as shown in FIG. 2b. Next, as shown in FIG. 2c, the second oxide layer 4 and the second polysilicon layer 5 are etched at a right angle to the floating gate 3a to form an interpoly dielectric layer 4a and a control gate 5a. Simultaneously, the tunnel oxide layer 2a and the floating gate 3a are etched. Subsequently, a photoresist layer 6 is coated on the entire surface and then is subjected to exposure and development to be patterned until the surface of the substrate for the placement of a source region is exposed. Thereafter, lightly-doped source impurity ions are implanted into the exposed substrate 1, which is then annealed for diffusion to form a lightly-doped source region 7.
Referring to FIG. 2d, the remaining photoresist layer 6 is removed. Next, a third oxide layer is formed and then subjected to etch-back to form insulating sidewalls 8 at both the sides of the control gate 5a and of the floating gate 3a. As shown in FIG. 2d, with the control gate 5a and the floating gate 3a serving as masks, heavily-doped impurity ions are implanted into the exposed substrate 1 to form the source and drain regions 9. Then, an interlayer insulating layer 10 is formed on the entire surface.
Referring to FIG. 2e, the interlayer insulating layer 10 is anisotropically etched to expose the source and drain regions 9 to form contact holes. Next, a wiring layer 11 of a conductive metal is formed in each of the contact holes.
Programming data in the related art semiconductor memory device is achieved by a process of injecting into a floating gate high thermal electrons made in a channel. As the programming proceeds, a threshold voltage is increased because of electrons accumulated in the floating gate.
Programming efficiency greatly depends on a voltage induced to the floating gate. Also, programming efficiency is improved as a coupling ratio, which is an induced voltage ratio of the floating gate relative to an applied voltage of the control gate, is increased.
Erasing data in a semiconductor memory device is achieved by a process of removing electrons from the floating gate 3a to the source region. Since electrons are taken out of the floating gate 3a, a threshold voltage of a cell is decreased. The operation to erasing data is performed by moving electrons from the floating gate 3a to the source region by F-N tunneling. In a related art method, a thin tunnel oxide layer 2a is used to increase erasing efficiency.
However, a related art semiconductor memory device has various disadvantages and problems. A thickness of a tunnel oxide layer becomes thin to improve efficiency of erasing data. When the tunneling oxide layer becomes thin, electrostatic capacities of a floating gate and a channel are increased, so that a coupling ratio of a cell is reduced. As a result, programming data efficiency is reduced
Since erasing operations are repeated more than 0.1 million times, the efficiency of erasing data is reduced because of thinness of the tunnel oxide layer. Accordingly, the process of forming a tunnel oxide layer is difficult and good reliability of a device is difficult to achieve. Moreover, data programmed in a memory cell can be erased by a low drain voltage.
The source region should be deeply diffused so the source junction is not destroyed because of a voltage applied to the source region for erasing data. Thus, a size of the device is enlarged, which reduces the degree of integration. Since a process tolerance should be provided to prevent shorts between the contact wire and the floating gate, the design of a semiconductor memory device and its manufacturing process also become difficult.